Sunday, September 28, 2014

1st look at Buck modeling

One of the 1st steps I want to do is some efficiency modeling; there are a few alternatives for hardware configurations - and some work up front can help select, or solidify, a direction.

I am using one of the .xls spreadsheets out there to model the standard CCM buck switching power supply architecture, as that architecture is rather simple and very mature in its development.  The one tool I was able to easily download (for some reason the .xls files are kind of hidden by many venders - even though the .pdf instructions are simple to find).   But I was able to locate the one from MicroChip.  Look under the Reference tab above for "AN01471A", both the .pdf and a .zip file with the spread sheet to save yourself a bit of googling :-)

The 1st thing I did was enter the devices used in this TI 20A-MPPT reference design:
It uses two paralleled buck sections which can have some issues of balancing between the two sections.  For the modeling I ran things up to 15A, just to cover the potential for uneven distribution of currents between the two.  

FYI:  I am using the TI reference design as they have well characterized the results, but am really only interested in the power (driver) side.  The CPU side seems a mess, including using RCs to delay digital signals to set the dead-time between the upper and lower FET.  Will not be doing that...

OK, so TI claims a measured 97% efficiency in a 12v deployment.  Putting in the power side components used, the MicroChip tool comes up with this graph:

I ran two curves.  One at 200K as the reference design was designed around, and one at 50Khz - which often result sin greater efficiency due to lower FET switching loss (esp the upper FET).  In this case, it did - esp at lighter loads.  But do keep in mind the design was not optimized for 50Khz, (Notably the FET), and there may be some problems with this - as well as additional opportunities.

And here is the table behind the graph:

Efficiency Graph

Series 1 2
Input Voltage (V) 17.33 17.33
Output Voltage (V) 12.32 12.32
Switching Frequency (Hz) 200000.00 50000.00
Driver VDD (V) 10.00 10.00
HS FET CSD18532Q5B CSD18532Q5B
LS FET CSD18532Q5B CSD18532Q5B
Driver SM72295MA SM72295MA
Inductor SER2915L-103KL SER2915L-103KL

Iout Efficiency
.000 00.00% 00.00%
.500 91.06% 97.37%
1.000 95.20% 98.61%
1.500 96.65% 99.02%
2.000 97.38% 99.21%
2.500 97.81% 99.32%
3.000 98.10% 99.39%
3.500 98.29% 99.43%
4.000 98.44% 99.46%
4.500 98.54% 99.47%
5.000 98.62% 99.48%
5.500 98.69% 99.48%
6.000 98.73% 99.48%
6.500 98.77% 99.47%
7.000 98.80% 99.46%
7.500 98.82% 99.45%
8.000 98.83% 99.44%
8.500 98.84% 99.43%
9.000 98.85% 99.41%
9.500 98.85% 99.40%
10.000 98.85% 99.38%
10.500 98.84% 99.36%
11.000 98.83% 99.34%
11.500 98.83% 99.32%
12.000 98.81% 99.30%
12.500 98.80% 99.28%
13.000 98.78% 99.26%
13.500 98.76% 99.23%
14.000 98.74% 99.21%
14.500 98.72% 99.18%
15.000 98.70% 99.15%

At 1st blush I would say there is an OK correlation between the calculations and the measurements, though the tool seems to be a bit more optimistic:   98.8% efficient at 7.5A (shared, 15A total)  vs. a 96.9% measured with the sample system.  But there is one key differeance here, the .xls modeling tool does not take into account the additional losses associated with the TI's platforms additional FETs on the input and outputs.  I iwll modify the tool some and see how much changes..

But overall it is perhaps a bit encouraging.  Tools seems somewhat close, at least with a couple of % not taking into account the additional losses in the actual hardware.  It also confirms the gains associated with lower frequencies.   Over the next week or so I want to play with different FET / Inductor combinations and see what can be produced.   As well as modifying the tool to include the ability to consider losses associated with Amp shunts, protection Diodes, and perhaps on/off FETs.

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