Tuesday, October 7, 2014

More in-depth look at Buck modeling - and some component selections

I have been playing more with the .xls buck modeling tool from MicroChip, plugging in various inductors and FETs to see what might be possible, along with varying the switching frequency to see its impact.  In short - FETs have made progress in the past few years.  Several of the ones I am looking at were released withing the year, and a few just this past summer.  Very low Rd-on's, and modest Qc's all help to reduce losses.  And as far as losses go, there really are three sources:
  • Series Resistance of the Inductor
  • Series Resistance of the FETs (Rd-on)
  • Switching losses of the FETs.

Like many things in life, choices are not simple - often balancing one side against another.  Take the Inductor:  Once sized for the max current (25A goal), inductance requirements actually increase as loads are reduced - less one lives wiht increased output ripple, or need to fall out of the common CCM mode into a less efficient DCM (Continuous Conduction Mode and Discontinuous Conduction Mode).  But with increase inductance comes increased resistance, opposing goals.  Sourcing a more expensive inductor can help solve this dilemma, as can increasing the switching frequency, but then we get more switching losses in the FETs.

And the FETs also have conflicts themselves - low Rd-on often comes with increased capacitance (ala, gate capacitance - Qg) that slows down switching times - increasing switching losses.

How to address this all?   Here is my current thinking:
  • Minimize conductive losses by using right sized inductor
    • Consider using variable frequency at lighter loads to remain in CCM mode
    • Accept larger Vout ripply for the battery charger then one would desire for a power supply
    • (Need to watch out for heating / losses on output caps though as they handle more ripple)
  • Minimize FET losses by:
    • Selecting low Rd-on devices
    • Balancing this with capacitance
    • use powerful driver chips to shorten switching times (ala, 4A drivers)
    • Design around 50Khz  primary operating frequency to lower accumulated switching losses even more.

Using the above approach, here is one example modeling results.  Design support  using the following components - with the resulting efficiency graph:
  • SER2915H-153KL  Inductor - Widely used Coilcraft 22uH inductor
  • LM25101C              Driver chip (Limits panels to 85 Voc max)
  • IRFH7185PbF         FETs - High and Low

 For some details, here is the data behind this graph:
(Click for larger view)

Hey, not bad!  Lots of 99%, and only drops to the high 98% under high load.  Do remember, this modeler only considers losses from the FETs, Inductor, and Driver chip.  Not included is the controller, Amp shunts, nor any reverse polarity losses.  Remember, this modeler predicted 98.8% against the measured(whole system) 96.9% of the TI reference design. 

 And by playing with different FETs, even looking at asymmetrical ones for the Top and Bottom FETs I was able to get another 0.5% out of this.  Bottom line:  A buck converter using modern FETs and coils can give very good efficiencies. A few concerns with the above components though:
  1. The Coilcraft inductor saturates at 11.5A.  Changing to a CWS HF467-260M-45AV solves this issue, but we loose about 0.5% efficiency and costs increase from $3.33ea to $23.50ea.
  2. FET driver limits panels to Voc of 85v, would like to see a bit higher voltage to match the FETs (100v) - just to get some more headroom on two large panels in series.
  3. FETs as shown use a very hard to hand-solder PQFN package. 
Moving to TO-220 parts (ala, an asymmetrical paring of: CSD19532Q5B & CSD19535Q5B) still delivers efficiency in the 98.7% range, but increases the pair cost from say $7.50 to $10 + the cost of a small heatsink.

No comments:

Post a Comment